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ultrafast 3.3 v/5 v single-supply sige comparators adcmp572/adcmp573 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2009 analog devices, inc. all rights reserved. features 3.3 v/5.2 v single-supply operation 150 ps propagation delay 15 ps overdrive and slew rate dispersion 8 ghz equivalent input rise time bandwidth 80 ps minimum pulse width 35 ps typical output rise/fall 10 ps deterministic jitter (dj) 200 fs random jitter (rj) on-chip terminations at both input pins robust inputs with no output phase reversal resistor-programmable hysteresis differential latch control extended industrial ?40c to +125c temperature range applications clock and data signal restoration and level shifting automatic test equipment (ate) high speed instrumentation pulse spectroscopy medical imaging and diagnostics high speed line receivers threshold detection peak and zero-crossing detectors high speed trigger circuitry functional block diagram v p noninverting input v tp termination v tn termination v n inverting input le input hys q output q output le input 04409-025 adcmp572 adcmp573 cml/ rspecl v cco v cci figure 1. general description the adcmp572 and adcmp573 are ultrafast comparators fabricated on analog devices proprietary xfcb3 silicon germanium (sige) bipolar process. the adcmp572 features cml output drivers and latch inputs, and the adcmp573 features reduced swing pecl (rspecl) output drivers and latch inputs. both devices offer 150 ps propagation delay and 80 ps minimum pulse width for 10 gbps operation with 200 fs rms random jitter (rj). overdrive and slew rate dispersion are typically less than 15 ps. a flexible power supply scheme allows both devices to operate with a single 3.3 v positive supply and a ?0.2 v to +1.2 v input signal range or with split input/output supplies to support a wider ?0.2 v to +3.2 v input signal range and an independent range of output levels. 50 on-chip termination resistors are provided at both inputs with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance inputs. the cml output stage is designed to directly drive 400 mv into 50 transmission lines terminated to between 3.3 v to 5.2 v. the rspecl output stage is designed to drive 400 mv into 50 terminated to v cco ? 2 v and is compatible with several commonly used pecl logic families. the comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. high speed latch and programmable hysteresis features are also provided. the adcmp572 and adcmp573 are available in a 16-lead lfcsp package and have been characterized over an extended industrial temperature range of ?40c to +125c.
adcmp572/adcmp573 rev. a | page 2 of 16 table of contents electrical characteristics ................................................................. 3 ? absolute maximum ratings ............................................................ 5 ? thermal considerations .............................................................. 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? application information .................................................................. 9 ? power/ground layout and bypassing ....................................... 9 ? cml/rspecl output stage ....................................................... 9 ? using/disabling the latch feature ..............................................9 ? optimizing high speed performance ..................................... 10 ? comparator propagation delay dispersion ........................... 10 ? comparator hysteresis .............................................................. 11 ? minimum input slew rate requirements .............................. 11 ? typical application circuits ......................................................... 12 ? timing information ....................................................................... 13 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 14 ? revision history 4/09rev. 0 to rev. a changes to figure 26 ...........................................................................12 updated outline dimensions ............................................................14 changes to ordering guide ...............................................................14 4/05revision 0: initial version
adcmp572/adcmp573 rev. a | page 3 of 16 electrical characteristics v cci = v cco = 3.3 v, t a = ?40c to +125c, typical at t a = +25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit dc input characteristics input voltage range v p , v n v cci = 3.3 v, v cco = 3.3 v ?0.2 +1.2 v v cci = 5.2 v, v cco = 3.3 v ?0.2 +3.1 v input differential voltage ?1.2 +1.2 v input offset voltage v os ?5.0 2.0 +5.0 mv offset voltage tempco ?v os /dt 10.0 v/c input bias current i p , i n open termination ?50.0 ?25.0 0.0 a input bias current tempco 50.0 na/c input offset current 2.0 a input impedance 50 input resistance, differential open termination 50 k input resistance, common-mode open termination 500 k active gain a v 54 db common-mode rejection cmrr v cci = 3.3 v, v cco = 3.3 v, v cm = 0.0 v to 1.0 v 65 db v cci = 5.2 v, v cco = 3.3 v, v cm = 0.0 v to 3.0 v 65 db power supply rejectionv cci psr vcci v cci = 3.3 v 5%, v cco = 3.3 v 74 db hysteresis r hys = 1 mv latch enable characteristics adcmp572 latch enable input range 2.8 v cco + 0.2 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 100 mv 15 ps latch hold time t h v od = 100 mv 5 ps adcmp573 latch enable input range 1.8 v cco ? 0.6 v latch enable input differential 0.2 0.4 0.5 v latch setup time t s v od = 100 mv 90 ps latch hold time t h v od = 100 mv 100 ps latch enable input impedance 50.0 latch to output delay t ploh, t plol v od = 100 mv 150 ps latch minimum pulse width t pl v od = 100 mv 100 ps dc output characteristics adcmp572 (cml) output impedance z out ?8 ma < i out < 8 ma 50.0 output voltage high level v oh 50 terminate to v cco v cco ? 0.10 v cco ? 0.05 v cco v output voltage low level v ol 50 terminate to v cco v cco ? 0.60 v cco ? 0.45 v cco ? 0.30 v output voltage differential 50 terminate to v cco 300 375 450 mv adcmp573 (rspecl) output voltage high ?40c v oh 50 terminate to v cco ? 2.0 v cco ? 1.14 v cco ? 1.02 v cco ? 0.90 v output voltage high +25c v oh 50 terminate to v cco ? 2.0 v cco ? 1.10 v cco ? 0.98 v cco ? 0.86 v output voltage high +125c v oh 50 terminate to v cco ? 2.0 v cco ? 1.04 v cco ? 0.92 v cco ? 0.80 v output voltage low ?40c v ol 50 terminate to v cco ? 2.0 v cco ? 1.54 v cco ? 1.39 v cco ? 1.24 v output voltage low +25c v ol 50 terminate to v cco ? 2.0 v cco ? 1.50 v cco ? 1.35 v cco ? 1.20 v output voltage low +125c v ol 50 terminate to v cco ? 2.0 v cco ? 1.44 v cco ? 1.29 v cco ? 1.14 v output voltage differential 50 terminate to v cco ? 2.0 300 375 450 mv
adcmp572/adcmp573 rev. a | page 4 of 16 parameter symbol conditions min typ max unit ac performance propagation delay t pd v cci = 3.3 v, v od = 200 mv 150 ps v cci = 3.3 v, v od = 20 mv 165 ps v cci = 5.2 v, v od = 200 mv 145 ps propagation delay tempco ?t pd /dt 0.5 ps/c prop delay skewrising transition to falling transition v od = 200 mv, 5 v/ns 10 ps overdrive dispersion 50 mv < v od < 0.2 v, 5 v/ns 15 ps 10 mv < v od < 0.2 v, 5 v/ns 15 ps slew rate dispersion 2 v/ns to 10 v/ns, 250 mv od 15 ps pulse width dispersion 100 ps to 5 ns, 250 mv od 5 ps 10% C 90% duty cycle dispersion v cci = 3.3 v, 1 v/ns, 250 mv od 5 ps v cci = 5.2 v, 1 v/ns, 250 mv od 10 common-mode dispersion v od = 0.2 v, 0.0 v < v cm < 2.9 v 5 ps/v equivalent input bandwidth 1 bw eq 0.0 v to 250 mv input t r = t f = 17 ps, 20/80 8.0 ghz toggle rate >50% output swing 12.5 gbps deterministic jitter dj v od = 200 mv, 5 v/ns, prbs 31 ? 1 nrz, 4 gbps 10 ps v od = 200 mv, 5 v/ns, prbs 31 ? 1 nrz, 10 gbps 20 ps rms random jitter rj v od = 200 mv, 5 v/ns, 1.25 ghz 0.2 ps minimum pulse width pw min ?t pd /?pw < 5 ps, 200 mv od 100 ps pw min ?t pd /?pw < 10 ps, 200 mv od 80 ps rise time t r 20/80 35 ps fall time t f 20/80 35 ps power supply input supply voltage range v cci 3.1 5.4 v output supply voltage range v cco 3.1 5.4 v positive supply differential v cci ?v cco ?0.2 +2.3 v adcmp572 (cml) positive supply current i vcci + i vcco v cci = 3.3 v, v cco = 3.3 v, terminate 50 to v cco 44 52 ma v cci = 5.2 v, v cco = 5.2 v, terminate 50 to v cco 44 52 device power dissipation p d v cci = 3.3 v, v cco = 3.3 v, terminate 50 to v cco 140 165 mw v cci = 5.2 v, v cco = 5.2 v, terminate 50 to v cco 230 265 adcmp573 (rspecl) positive supply current i vcci + i vcco v cci = 3.3 v, v cco = 3.3 v, 50 to v cco ? 2 v 62 80 ma v cci = 5.2 v, v cco = 5.2 v, 50 to v cco C 2 v 64 80 device power dissipation p d v cci = 3.3 v, v cco = 3.3 v, 50 to v cco ? 2 v 110 160 mw v cci = 5.2 v, v cco = 5.2 v, 50 to v cco ? 2 v 146 230 1 equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: bw eq = 0.22/ (tr comp 2 ?tr in 2 ), where tr in is the 20/80 transition time of a quasi-gaussian signal applied to the comparator input, and tr comp is the effective transition time digitized by the comparator.
adcmp572/adcmp573 rev. a | page 5 of 16 absolute maximum ratings table 2. parameter rating supply voltage input supply voltage (v cci to gnd) ?0.5 v to +6.0 v output supply voltage (v cco to gnd) ?0.5 v to +6.0 v positive supply differential (v cci ? v cco ) ?0.5 v to +3.5 v input voltage input voltage ?0.5 v to v cci + 0.5 v differential input voltage (v cci + 0.5 v) input voltage, latch enable ?0.5 v to v cco + 0.5 v hysteresis control pin applied voltage (hys to gnd) ?0.5 v to +1.5 v maximum input/output current 1 ma output current adcmp572 (cml) 20 ma adcmp573 (rspecl) ?35 ma temperature operating temperature, ambient ?40c to +125c operating temperature, junction +150c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal considerations the adcmp572/adcmp573 lfcsp 16-lead package has a ja (junction-to-ambient thermal resistance) of 70c/w in still air. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adcmp572/adcmp573 rev. a | page 6 of 16 pin configuration and fu nction descriptions 04409-026 5 v cci 6 le 7 le 8 v cco /v tt adcmp572 adcmp573 top view (not to scale) 1 v tp pin1 2 v p 3 v n 4 v tn 16 v cci 15 gnd 14 hys 13 gnd v cco 12 q 11 q 10 v cco 9 figure 2. adcmp572/adcmp573 pin configuration table 3. pin function descriptions pin no. mnemonic description 1 v tp termination resistor return pin for v p input. 2 v p noninverting analog input. 3 v n inverting analog input. 4 v tn termination resistor return pin for v n input. 5, 16 v cci positive supply voltage for input stage. 6 le latch enable input pin, inverting side. in compare mode (le = low), the output tracks changes at the input of the comparator. in latch mode (le = high), the output reflects the input state just prior to the comparators being placed into latch mode. le must be driven in complement with le. 7 le latch enable input pin, noninverting side. in compare mode (le = high), the output tracks changes at the input of the comparator. in latch mode (le = low), the output reflects the input state just prior to the comparators being placed into latch mode. le must be driven in complement with le . 8 v cco /v tt termination return pin for the le/le input pins. for the adcmp572 (cml output stage), this pin is inte rnally connected to and a lso should be externally connected to the positive v cco supply. for the adcmp573 (rspecl output stage), this pi n should normally be connected to the v cco C 2 v termination potential. 9, 12 v cco positive supply voltage for the cml/rspecl output stage. 13, 15 gnd ground. 10 q inverting output. q is at logic low if the analog voltage at the noninverting input, v p , is greater than the analog voltage at the inverting input, v n , provided the comparator is in compare mode. see the le/le descriptions (pins 6 and 7) for more information. 11 q noninverting output. q is at logic high if th e analog voltage at the noninverting input v p is greater than the analog voltage at the inverting input, v n , provided the comparator is in compare mode. see the le/le descriptions (pins 6 and 7) for more information. 14 hys hysteresis control pin. leave this pin disconnected for zero hysteresis. connect to gnd with a suitably sized resistor to add the desired amount of hyst eresis. refer to figure 7 for proper sizing of r hys hysteresis control resistor. isolated heat sink n/c the metallic back surface of the package is not electric ally connected to any part of the circuit, and it can be left floating for best elec trical isolation between the packag e handle and the substrate of the die. however, it can be soldered to the applicat ion board if improved thermal and/or mechanical stability is desired. exposed metal at package corners is connected to the heat sink paddle.
adcmp572/adcmp573 rev. a | page 7 of 16 typical performance characteristics v cci = v cco = 3.3 v, t a = 25c, unless otherwise noted. propagation delay error (ps) 5 10 15 20 36.0 36.5 37.0 37.5 38.0 38.5 39.0 rise/fall time (ps) 20 0 ?40 ?20 ?60 40 60 80 100 temperature (c) 04409-042 0 0 50 100 150 200 250 input overdrive voltage (mv) 04409-039 figure 3. propagation delay vs. input overdrive 155.5 0.4 0.6 0 0.2 0.8 1.0 1.2 input common-mode voltage (v) 04409-040 156.0 156.5 157.0 157.5 158.0 158.5 propagation delay (ps) figure 4. propagation delay vs. input common-mode 146 20 0 ?40 ?20 ?60 40 60 80 100 temperature (c) 04409-041 148 150 152 154 156 158 160 propagation delay (ps) figure 5. propagation delay vs. temperature figure 6. rise/fall time vs. temperature 0 10 20 30 40 50 60 hysteresis (mv) 23 01 456 r hys (k ) 04409-043 figure 7. hysteresis vs. r hys control resistor r hys sink current ( a) hysteresis (mv) 80 70 40 30 50 60 20 10 0 ?600 ?500 ?400 ?300 ?200 ?100 0 04409-047 figure 8. hysteresis vs. r hys sink current
adcmp572/adcmp573 rev. a | page 8 of 16 ?18.5 ?18.0 ?17.5 ?17.0 ?16.5 ?16.0 ?15.5 ?15.0 input bias current ( a) ?0.5 ?0.3 ?0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 04409-044 v p input voltage (v n = ?0.2v) 373 374 375 376 377 378 379 380 output levels (mv) 20 0 ?40 ?20 ?60 40 60 80 100 temperature (c) 04409-046 figure 9. input bias current vs. input differential ?16.9 ?16.8 ?16.7 ?16.6 ?16.5 ?16.4 ?16.3 ?16.2 input bias current ( a) 20 0 ?40 ?20 ?60 40 60 80 100 04409-045 temperature (c) figure 10. input bias current vs. temperature temperature ( c) offset (mv) 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?50 0 50 100 75 25 ?25 125 04409-024 figure 11. input offset voltage vs. temperature figure 12. output levels vs. temperature 496.0mv m1 04409-049 504.0mv 60.00ps/div figure 13. adcmp572 eye diagram at 2.5 gbps 04409-050 500.0mv 500.0mv 25.00ps/div figure 14. adcmp572 eye diagram at 6.5 gbps
adcmp572/adcmp573 rev. a | page 9 of 16 application information power/ground layout and bypassing the adcmp572/adcmp573 comparators are very high speed sige devices. consequently, it is essential to use proper high speed design techniques to achieve the specified performance. of critical importance is the use of low impedance supply planes, particularly the output supply plane (v cco ) and the ground plane (gnd). individual supply planes are recom- mended as part of a multilayer board. providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. it is important to adequately bypass the input and output supplies. a 1 f electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. in addition, multiple high quality 0.01 f bypass capacitors should be placed as close as possible to each of the v cci and v cco supply pins and should be connected to the gnd plane with redundant vias. high frequency bypass capacitors should be carefully selected for minimum inductance and esr. parasitic layout inductance should be avoided to maximize the effectiveness of the bypass at high frequencies. if the input and output supplies are connected separately such that v cci v cco , care should be taken to bypass each of these supplies separately to the gnd plane. a bypass capacitor should not be connected between them. it is recommended that the gnd plane separate the v cci and v cco planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capacitance from each respective supply to the ground plane. this enhances the performance when split input/output supplies are used. if the input and output supplies are connected together for single-supply operation such that v cci = v cco , coupling between the two supplies is unavoidable; however, every effort should be made to keep the supply plane adjacent to the gnd plane to maximize the additional bypass capacitance this arrangement provides. cml/rspecl output stage specified propagation delay dispersion performance can be achieved only by using proper transmission line terminations. the outputs of the adcmp572 are designed to directly drive 400 mv into 50 cable, microstrip, or strip line transmission lines properly terminated to the v cco supply plane. the cml output stage is shown in the simplified schematic diagram of figure 15 . the outputs are each back terminated with 50 for best transmission line matching. the rspecl outputs of the adcmp573 are illustrated in figure 16 and should be terminated to v cco ? 2 v. as an alternative, thevenin equivalent termination networks can be used in either case if the direct termination voltage is not readily available. if high speed output signals must be routed more than a centimeter, microstrip or strip line techniques are essential to ensure proper transition times and to prevent output ringing and pulse width dependent propagation delay dispersion. for the most timing critical applications where transmission line reflections pose the greatest risk to performance, the adcmp572 provides the best match to 50 output transmission paths. q 16ma 50 q 04409-037 v cco gnd figure 15. simplified schematic diagram of the adcmp572 cml output stage 04409-038 v cco gnd q q figure 16. simplified schematic diagram of the adcmp573 rspecl output stage using/disabling the latch feature the latch inputs (le/ le ) are active low for latch mode and are internally terminated with 50 resistors to pin 8. this pin corresponds to and is internally connected to the v cco supply for the cml-compatible adcmp572. with the aid of these resistors the adcmp572 latch function can be disabled by connecting the le pin to gnd with an external pull-down resistor and leaving the le pin unconnected. to avoid excessive power dissipation, the resistor should be 750 when v cco = 3.3 v, and 1.2 k when v cco = 5.2 v. in the pecl-compatible adcmp573, the v tt pin should be connected externally to the pecl termination supply at v cco C 2 v. the latch can then be disabled by connecting the le pin to v cco with an external
adcmp572/adcmp573 rev. a | page 10 of 16 500 resistor and leaving the le pin disconnected. in this case, the resistor value does not depend on the v cco supply voltage. v cco is the signal return for the output stage and v cco pins should of course be connected to a supply plane for maximum performance. optimizing high speed performance as with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. discontinuities along input and output transmission lines can severely limit the specified pulse width dispersion performance. for applications working in a 50 environment, input and output matching has a significant impact on data dependent (or deterministic) jitter (dj) and on pulse width dispersion performance. the adcmp572/adcmp573 comparators provide internal 50 termination resistors for both the v p and v n inputs, and the adcmp572 provides 50 back terminated outputs. the return side for each input termination is pinned out separately with the v tp and v tn pins, respectively. if a 50 termination is desired at one or both of the v p /v n inputs, then the v tp and v tn pins can be connected (or disconnected) to (from) the desired termination potential as required. the termination potential should be carefully bypassed using high quality bypass capacitors as discussed earlier to prevent undesired aberrations on the input signal due to parasitic inductance in the circuit board layout. if a 50 input termination is not desired, either one or both of the v tp /v tn termination pins can be left disconnected. in this case, the pins should be left floating with no external pull-downs or bypassing capacitors. when leaving an input termination disconnected, the internal resistor acts as a small stub on the input transmission path and can cause problems for very high speed inputs. reflections should then be expected from the comparator inputs because they no longer provide matched impedance to the input path leading to the device. in this case, it is important to back match the drive source impedance to the input transmission path to minimize multiple reflections. for applications in which the comparator is very close to the driving signal source, the source impedance should be minimized. high source impedance in combination with parasitic input capacitance of the comparator might cause an undesirable degradation in bandwidth at the input, therefore degrading the overall response. although the adcmp572/ adcmp573 comparators have been designed to minimize in put capacitance, some parasitic capacitance is inevitable. it is therefore recommended that the drive source impedance be no more than 50 for best high speed performance. comparator propagation delay dispersion the adcmp572/adcmp573 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mv to 500 mv. propagation delay dispersion is variation in the propagation delay that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). propagation delay dispersion is a specification that becomes important in high speed, time-critical applications such as data communication, automatic test and measurement, instrumenta- tion, and event driven applications such as pulse spectroscopy, nuclear instrumentation, and medical imaging. dispersion is defined as the variation in propagation delay as the input over- drive conditions vary ( figure 17 and figure 18 ). for the adcmp572/adcmp573, dispersion is typically <15 ps because the overdrive varies from 10 mv to 500 mv, and the input slew rate varies from 2 v/ns to 10 v/ns. this specification applies for both positive and negative signals since the adcmp572/ adcmp573 has substantially equal delays for ei ther positive going or negative going inputs. q/q output input voltage 500mv overdrive 10mv overdrive dispersion v n v os 04409-0-027 figure 17. propagation delayoverdrive dispersion q/q output input voltage 10v/ns 1v/ns dispersion v n v os 04409-0-028 figure 18. propagation delayslew rate dispersion
adcmp572/adcmp573 rev. a | page 11 of comparator hysteresis the addition of hysteresis to a comparator is often desirable in a noisy environment or when the differential input amplitudes are relatively small or slow moving, but excessive hysteresis has a cost in degraded accuracy and slew-induced timing shifts. the transfer function for a comparator with hysteresis is shown in figure 19 . if the input voltage approaches the threshold (0.0 v in this example) from the negative direction, the comparator switches from low to high when the input crosses +vh/2. the new switching threshold becomes ?v h /2. the comparator remains in the high state until the threshold ?v h /2 is crossed from the positive direction. in this manner, noise centered on 0.0 v input does not cause the comparator to switch states unless it exceeds the region bounded by v h /2. 16 output v ol v oh input 0 +v h 2 ?v h 2 04409-005 figure 19. comparator hysteresis transfer function the customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. a limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that can be load dependent and is not symmetrical about the threshold. the external feedback network can also introduce significant parasitics, which reduce high speed performance and can even induce oscillation in some cases. the adcmp572/adcmp573 comparators offer a program- mable hysteresis feature that can significantly improve the accuracy and stability of the desired hysteresis. by connecting an external pull-down resistor from the hys pin to gnd, a variable amount of hysteresis can be applied. leaving the hys pin disconnected disables the feature, and hysteresis is then less than 1 mv as specified. the maximum hysteresis that can be applied using this method is approximately 25 mv with the pin grounded. figure 20 illustrates the amount of hysteresis applied as a function of external resistor value. the advantages of applying hysteresis in this manner are improved accuracy, stability, and reduced component count. an external bypass capacitor is not recommended on the hys pin because it would likely degrade the jitter performance of the device. the hysteresis pin could also be driven by a cmos dac. it is biased to approximately 250 mv and has an internal series resistance of 600 . 0 10 20 30 40 50 60 hysteresis (mv) 23 01 456 r hys (k ) 04409-043 figure 20. hysteresis vs. r hys control resistor minimum input slew rate requirements as with all high speed comparators, a minimum slew rate requirement must be met to ensure that the device does not oscillate as the input signal crosses the threshold. this oscillation is due in part to the high input bandwidth of the comparator and the feedback parasitics inherent in the package. a minimum slew rate of 50 v/s should ensure clean output transitions from the adcmp572/ adcmp573 comparators. the s lew rate may be too slow for other reasons. the extremely high bandwidth of these devices means that broadband noise can be a significant factor when input slew rates are low. there will be at least 120 v of thermal noise generated over the full comparator bandwidth by two 50 terminations at room temperature. with a slew rate of only 50 v/s the input will be inside this noise band for over 2 ps, rendering the comparators jitter performance of 200 fs moot. raising the slew rate of the input signal and/or reducing the bandwidth over which this resistance is seen at the input can greatly reduce jitter.
adcmp572/adcmp573 rev. a | page 12 of 16 typical application circuits q 3.3v 50 50 adcmp572 q v in v p v tp v tn v n latch inputs 04409-034 v cci latch inputs 04409-029 v cci v cco figure 21. zero-crossing detector with 3.3 v cml outputs q 50 50 q v p v n v p v tp v tn v n v cco = 3.3v 5v 75 50 50 100 100 adcmp572 figure 25. interfacing 3.3 v cml to a 50 ground terminated instrument latch inputs 04409-030 v cci = 5.2v adcmp572 v cco figure 22. lvds to 50 back terminated rspecl receiver 50 50 + ? q q v in v th latch v cci v p v n v cco = 3.3v v cco v cco adcmp572 50? 1.35k ? 50? 0 4409-035 figure 26. disabling the adcmp572 latch feature inputs gnd = ?1v 04409-031 v cci = 3.3v v cco = 2.5v/3.3v 2.5v/3.3v adcmp572 figure 23. comparator with 1 v input range and 2.5 v or 3.3 v cml outputs 50 50 q q v in v th v p v n 500 04409-048 v cci = 5.2v = v cco v tt = 3.2v v cco adcmp573 50 50 figure 27. disabling the adcmp573 latch feature latch inputs 04409-032 v cci = 5.2v v cco = 3.3v/5.2v 3.3v/5.2v adcmp572 figure 24. comparator with 0 v to 3 v input range and 3.3 v or 5.2 v positive cml outputs hys v cco v cco 04409-036 v cci adcmp572 50 50 0 to 5k figure 28. adding hysteresis using the hys control pin
adcmp572/adcmp573 rev. a | page 13 of 16 timing information figure 29 illustrates the adcmp572/adcmp573 compare and latch timing relationships. table 4 provides definitions of the terms shown in the figure. 50% 50% v n v os 50% differential input voltage latch enable q output q output latch enable t h t pdl t pdh t ploh t plol t r t f v in v od t s t pl 04409-003 figure 29. system timing diagram table 4. timing descriptions symbol timing description t pdh input to output high delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. t pdl input to output low delay propagation delay measured from the time th e input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. t ploh latch enable to output high delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. t plol latch enable to output low delay propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. t h minimum hold time minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. t pl minimum latch enable pulse width minimum time that the latch enable signal must be high to acquire an input signal change. t s minimum setup time minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. t r output rise time amount of time required to transition from a low to a high output as measured at the 20% and 80% points. t f output fall time amount of time required to transition from a high to a low output as measured at the 20% and 80% points. v od voltage overdrive difference between the input voltages v a and v b .
adcmp572/adcmp573 rev. a | page 14 of 16 outline dimensions 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 3.00 bsc sq 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 30. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters ordering guide model temperature range package desc ription package option branding adcmp572bcp-wp ?40c to +85c 16-lead lfcsp_vq cp-16-2 g03 adcmp572bcpz-wp 1 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g0y adcmp572bcp-r2 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g03 adcmp572bcp-rl7 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g03 adcmp572bcpz-r2 1 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g0y adcmp572bcpz-rl7 1 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g0y adcmp573bcp-wp ?40c to +85c 16-lead lfcsp_vq cp-16-2 g05 adcmp573bcpz-wp 1 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g0z adcmp573bcp-r2 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g05 adcmp573bcp-rl7 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g05 adcmp573bcpz-r2 1 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g0z adcmp573bcpz-rl7 1 ?40c to +85c 16-lead lfcsp_vq cp-16-2 g0z eval-adcmp572bcpz 1 evaluation board EVAL-ADCMP573BCPZ 1 evaluation board 1 z = rohs compliant part.
adcmp572/adcmp573 rev. a | page 15 of 16 notes
adcmp572/adcmp573 rev. a | page 16 of 16 notes ? 2005C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04409C0C4/09(a)

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